Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits
نویسندگان
چکیده
In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, we have obtained a program that, for different technologies, can quickly translate a large layout into an equivalent network. The network includes layout parasitics of the interconnects and can directly be simulated by various simulation packages, such as Spice. The efficiency and accuracy of the extractor are confirmed by experimental results and enable a fast and reliable layout verification for both MOS and bipolar/BiCMOS technologies.
منابع مشابه
Bipolar Device Modeling for VLSI Layout Verification
Today, layout verification for VLSI is a crucial part of IC design. However, for applicability, this must be both fast and accurate. Layout-to-circuit extractors can meet both these constraints. They quickly convert a layout into an equivalent network that accurately models that layout. Subsequently, circuit simulation and network comparison are convenient tools that enable accurate prediction ...
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